An analog signal switch is generally formed by a metal oxide semiconductor (MOS) transistor, the source forming the input terminal and the drain forming the output terminal. To close the switch, i.e. render the transistor conductive, a gate-source voltage Vgs exceeding the threshold voltage Vt of the transistor is normally applied. In addition, to obtain the lowest possible resistance when the transistor is in the conductive state, it is sought to apply the highest possible constant gate-source voltage within the limits of the transistor manufacturing technology. As the source voltage is variable, the “bootstrap” technique is used, which comprises pre-charging a capacitor to the highest possible voltage, and applying the voltage of this capacitor between the gate and source of the transistor to render it conductive.
FIG. 1 shows an example of the “bootstrap” technique for the control of the power stage of a DC-DC or DC-AC converter. For example, the L6385 circuit uses this structure, as available from STMicroelectronics, N.V. of Geneva, Switzerland. The power stage comprises two N-channel MOS transistors, MNH and MNL, connected in series between the power supply lines Vdd and Vss. Their interconnection point provides the output V1 of the stage. These transistors are controlled in phase opposition so as to alternately bring the output V1 between the potentials Vdd and Vss with a desired duty factor.
For the high-side transistor MNH to be able to bring the terminal V1 to the potential Vdd, and have a low impedance, it may have a gate potential higher than Vdd. For that, a capacitor Cb is provided, having a low-side terminal connected to the source of the transistor MNH and a high-side terminal connected to the line Vdd by a diode D. The gate of the transistor MNH is controlled by a circuit 10 powered from the capacitor Cb.
The diode D is connected to be conductive when the output V1 is pulled toward the line Vss by the transistor MNH. The capacitor Cb thus charges to a voltage Vdd−Vt, where Vt is the threshold voltage of the diode D. When the output V1 is pulled toward the line Vdd, the potential on the high terminal of the capacitor Cb increases with the potential of the terminal V1, whereby the diode D is reverse biased and the capacitor Cb keeps its charge. Thus, the circuit 10 may control the transistor MNH with a voltage Vgs=Vdd−Vt, whatever the potential V1 on the transistor source.
This “bootstrap” structure, although simple and efficient, cannot be used in low voltage applications, because the threshold Vt of the diode D, around 0.6 V, is too high with respect to the power supply voltage Vdd, for example, 1.2 V, used in these applications. The result is that the voltage reached across the capacitor Cb is insufficient to control the switching transistor.
Analog-to-digital converters, generally integrated with the digital circuits they drive, are made with the densest technologies. In these technologies, the transistors are particularly sensitive to fatigue or “stress” phenomena, due to excess of the nominal operating voltage. These phenomena tend to deteriorate the gate oxides of the transistors, rendering them conductive little by little. Two types of transistors, which can be made on a same integrated circuit, are then provided: the transistors having single gate oxide thickness, called GO1, and the transistors having double gate oxide thickness, called GO2. For the technological nodes of 90, 65 and 40 nm, the nominal voltages of the transistors GO1 and GO2 are around 1.2 V and 2.5 V, respectively. GO1 transistors have better characteristics, in particular, as to their on-resistance (Ron) and cutoff frequency. Thus, GO2 transistors are only used as a last resort.
FIG. 2 shows a typical principle allowing the “bootstrap” technique to be used in low voltage applications. The terminals of the capacitor Cb are connected by respective switches S1 and S2 to the power supply lines Vdd and Vss. Switches S3 and S4 connect the terminals of the capacitor Cb respectively to the gate and source of the switching transistor MN1, of N-channel MOS type. The source of the transistor MN1 forms the input terminal V1 of the analog signal to be switched, and the drain forms the output terminal V2 of the switch. A switch S5 connects the gate of the transistor MN1 to the line Vss. The substrate of transistor MN1 is connected to the line Vss, the lowest available potential, so as to reduce the threshold voltage Vt of the transistor.
To control the opening of transistor MN1, switches S1, S2 and S5 are closed, and switches S3 and S4 are opened. The capacitor Cb is charged at the voltage Vdd, provided that switches S1 and S2 have a low voltage drop. The gate of transistor MN1 is connected to the line Vss, normally at a potential lower than V1, that of the transistor source. This inversion of voltage Vgs of transistor MN1 is desirable to minimize leakage current and guarantee that the voltage Vgs remains low enough for the minimum values of the input signal applied to the terminal V1.
To control the closing of transistor MN1, switches S1, S2 and S5 are opened, and switches S3 and S4 are closed, as shown. The capacitor Cb is connected between the gate and source of transistor MN1 and applies a voltage Vgs=Vdd. To have sufficient dynamics for an analog-to-digital conversion, the analog signal to be switched V1 has a peak-to-peak deviation around 1 V, and its common mode is around 1.2 V. The result is that, taking into account the usual margins of tolerance, the voltage V1 may reach 1.8 V, and therefore exceed the nominal power supply voltage of GO1 transistors. The structure of FIG. 2 is therefore built with GO2 transistors and powered under Vdd=2.5 V.
FIG. 3 is a detailed diagram of a switching circuit implementing the principle of FIG. 2, as described by the article “A 1.5V, 10-bit, 14.3-MS/s CMOS Pipeline Analog-to-Digital Converter,” Andrew M. Abo and Paul R. Gray, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 34, NO. 5, MAY 1999. In this circuit, the elements of FIG. 2 have been identified.
This circuit will not be described in detail, but the complexity thereof can be noted. This complexity mainly results from the fact that the maximum voltage reached in the circuit, by the high-side terminal of the capacitor Cb, is around 4.3 V (1.8 V for the voltage V1 plus 2.5 V for the voltage across the capacitor Cb). This voltage exceeds the nominal voltage of GO2 transistors, and various precautions are taken to “protect” the stressed transistors. For example, the switch S5 is formed by two cascoded transistors. The gate of the P-channel MOS transistor forming the switch S3 cannot be connected to the line Vss to render this transistor conductive—for that, a three-transistor circuit has been provided to connect this gate to the low-side terminal of the capacitor Cb.
In addition, the switch S1 is formed by an N-channel MOS transistor requiring a gate potential higher than the potential Vdd so that the high terminal of the capacitor Cb may be brought to Vdd. A charge pump is provided to that end, shown at the left of the transistor S1. The reason why an N-channel transistor has been chosen for the switch S1 is that a P-channel transistor would have, at the level of its substrate-drain junction, a forward biased diode between the high-side terminal of the capacitor Cb and the line Vdd, limiting the potential of this terminal to Vdd+Vt. The switching transistor MN1 has a dual gate oxide thickness, and its characteristics in terms of on-resistance are not optimum.